Pipeline Hazards
Pipelined architecture hides CPU latency. However, there are cases known as pipeline hazards where CPUs can’t executing next instruction in the following clock cycle.
There are multiple kinds of pipeline hazards:
- structural hazard: multiple instructions competing the same part of the CPU
- data hazard: CPU is waiting an operand to be computed in the previous step
- control hazard: CPU can’t tell which instruction to execute next
Pipeline hazards cause pipeline stall, where CPU need to wait idle.
Control Hazard and the Cost of Branching
CPU performs speculated execution when facing branching, so the performance of branching highly depends on how well the CPU can predict the branch. In a 50/50 coin toss, the CPU will meet control hazard since it doesn’t know what branch to execute next. We can use branchless programming to avoid branching in hot paths.